Certificate Course on Chip Design & FPGA System Design (CDFD-2024)/Faculty Development Program on Chip Designing /Internship on VLSI Design

 

 

Dear Sir/Madam,

We are pleased to share that Indian Society for VLSI Education(ISVE) Ranchi is organizing Certificate Course on Chip Design & FPGA System Design(CDFD-2024) /Faculty Development Program on Chip Designing / Internship on VLSI Design under ages of India Semiconductor Mission(ISM)  from 5th Feb 2023 to 5th Dec 2024 in Virtual Mode(Online Mode) for preparing the trained manpower in VLSI Design & Embedded Systems  with following Academic Universities, Institutions and Industries: 

SN

Name of Universities/ Institutions/Industries

Name of Coordinators/ Co-Organizers

1.

School of Studies in Electronics & Photonics & Institute of Renewable Energy Technology & Management

Pt. Ravishankar Shukla University Raipur (CG)

Dr. Kavita Thakur

Professor & Head

2.

Department of Electronics

Shri. Shivaji Vidyaprasarak Sanstha's

Bapusaheb Shivajirao Deore College of Engineering, Dhule.

Dr. Sagar A. More

Associate Professor

 

3.

 

 

4.

 

 
     

 

 

There are huge demand of trends power in this area. Number of core companies, startups and Educational Institutions are seeking the trained manpower in this domain.

Lecture will be delivered by subject experts from Industry and Academia. Classes will be from 6:00pm to 7:30pm (Monday to Friday).  It will cover theory with practical. 

Courses are offered module wise by Monday to Friday, some special classes will be offered Saturday or Sunday as per needs. Interested participants can register module wise, attend the lecture and do the practice on the related software. Job Guarantees  who will be completed all modules successfully.

Benefits to the Institutional Membership/ Student Chapters/ MoU with ISVE: A Institute who have Institutional Membership / Student Chapters/ MoU with ISVE Ranchi will get the 10% discount in their students /faculties fees.

Honorarium to Course Expert:

A faculty/ Scientist / Engineers who are involved in Certificate Course on Chip Design & FPGA System Design(CDFD-2024) / Faculty Development Program of Chip Designing / Internship on VLSI Design

will get the honorarium as per ISVE Rules. A person have abilities to teach the students at current job level can fill their consent in google sheet. Organizing committee will contact you for the same.

A list of VLSI Core Companies who are offering the Job in VLSI Design:

A list of companies and startups are seeking trained manpower for core VLSI Design work.

  1. https://www.naukri.com/vlsi-jobs
  2. https://in.linkedin.com/jobs/vlsi-design-jobs 
  3. https://in.linkedin.com/jobs/vlsi-jobs 
  4. https://www.maven-silicon.com/vlsi-jobs-for-freshers/ 
  5. https://www.glassdoor.co.in/Job/india-vlsi-design-jobs-SRCH_IL.0,5_IN115_KO6,17.htm
  6. https://www.rv-skills.com/career-opportunities-in-VLSI.php 

There are very good future of this area. 

About ISVE Ranchi : It is non profitable registered society dedicated to serve the nation. It makes a bridge between industry and academia for organizing the workshops, summer/winter schools, short term courses, conferences, symposiums and seminars by which students, research scholars, faculties and scientists come together, work together and share their knowledge in recent development in engineering, science & technology[www.isve.in]. 

 Registration:  Registration Form

1.      Registration fee includes conference kit & study materials. Participants have a special provision to select their training/ internship module wise. Now, Registration is open for all modules. Interested can select the module and register.

2.      Please download the Registration Form from the mail-attachment/website and send scan copy of filled Registration Form with NEFT receipt through e-mail for early registration. A/C Name: INDIAN SOCIETY FOR VLSI EDUCATION, A/C Number: 01670110061831, IFSC Code: UCBA0000167, Bank: UCO Bank, Branch: Mesra Ranchi, Address: BIT Main Building Mesra, Dist: Ranchi, State: Jharkhand, Contact No: 0651-2275829.

Certificate Course on Chip Design and FPGA System Design (CDFD-2024) / Faculty Development Program on Chip Designing /

Internship on VLSI Design

 Program Schedule & Fees Details

SN

Training Schedule

Category of Candidate & Fees

UG/PG/PhD

Indian Rs

Category of Candidate & Fees

Engineer/Faculty/Scientist

Indian Rs

1.

5 days

2000

4000

2.

10 days

4000

8000

3.

15 days

6000

12000

4.

20 days

8000

16000

5.

25 days

10000

20000

6.

30 days

12000

24000

7.

35 days

14000

28000

8.

40 days

16000

32000

9.

45 days

18000

36000

10.

50 days

20000

40000

11.

55 days

22000

44000

12

60 days

24000

48000

13

65 days

26000

52000

14

70 days

28000

56000

15

75 days

30000

60000

16

80 days

32000

64000

17

85 days

34000

68000

18

90 days

36000

72000

19

95 days

38000

76000

20

100 days

40000

80000

21

105 days

42000

84000

22

110 days

44000

88000

23

115 days

46000

92000

24

120 days

48000

96000

25

125 days

50000

100000

26

130 days

52000

104000

27

135 days

54000

108000

28

140 days

56000

112000

29

145 days

58000

116000

30

150 days

60000

120000

31

155 days

62000

124000

32

160 days

64000

128000

33

165 days

66000

132000

34

170 days

68000

136000

35

175 days

70000

140000

36

180 days

72000

144000

37

185 days

74000

148000

38

190 days

76000

152000

39

195 days

78000

156000

40

200 days

80000

160000

 

 

 

 

Course Syllabus: Attachment

Syllabus of Certificate Course of Chip Design & FPGA System Design (CDFD-2024)/ Faculty Development Program on Chip Designing/ Internship on VLSI Design

5 days to 200 days courses are available here for Certificate Course , Faculty Development Program and Internship here:

https://docs.google.com/document/d/1ZMxY9SHpu14qgPJV4ddrqjO_ZhJaIo-Q/edit?pli=1 

SN

Scheduled Date

Course Contents

           Certificate Course: Module 1

1

05.02.2024

Fundamentals of Chip Design

2

06.02.2024

Fundamentals of IC technologies

3

07.02.2024

Fundamentals of logic design

4

08.02.2024

Fundamentals of VHDL and Verilog

5

09.02.2024

Fundamentals of FPGA System Design

Certificate Course: Module 2

6

12.02.2024

Fundamentals of PN junction diode

7

13.02.2024

Design & Functionality of PN junction diode

8

14.02.2024

Fundamentals of MOSFET

9

15.02.2024

Design of MOSFET

10

16.02.2024

Functionality of MOSFET & its Characteristics

Certificate Course: Module 3

11

19.02.2024

PN Junction Diode as Half Wave Rectifier, Full Wave Rectifier (Bridge Rectifier, Centre Tapped Rectifier)

12

20.02.2024

Design of Zener Diode

13

21.02.2024

Application of Zener Diode as Regulator

14

22.02.2024

Design of JFET

15

23.02.2024

Functionality of JFET and its Characteristics

Certificate Course: Module 4

16

26.02.2024

Logic Gates Design using MOSFET

17

27.02.2024

Combinational Circuit Design using MOSFET (Mux, Demux)

18

28.02.2024

Combinational Circuit Design using MOSFET (Decoder, Encoder, ALU)

19

29.02.2024

Sequential Circuit Design using MOSFET (Flip-Flops)

20

01.03.2024

Sequential Circuit Design using MOSFET (Registers, Counters)

Certificate Course: Module 5

21

04.03.2024

Introduction to Boolean Algebra

22

05.03.2024

Introduction to Boolean Operators

23

06.03.2024

Symbolic Representation, Boolean Algebraic Function & Truth Table of Different Logic Gates

24

07.03.2024

Circuit Optimization Techniques by Boolean Axioms & K-Map

25

08.03.2024

Design of Basic Gates using Universal Gates

Certificate Course: Module 6

26

11.03.2024

Introduction of VHDL

27

12.03.2024

Important Terms of VHDL

28

13.03.2024

Digital Logic Design using VHDL

29

14.03.2024

Combinational Circuit Design using VHDL (Mux, Demu)

30

15.03.2024

Combinational Circuit Design using VHDL (Decoder, Encoder, ALU)

Certificate Course: Module 7

31

18.03.2024

Introduction to Verilog

32

19.03.2024

Programing of Verilog@HDL

33

20.03.2024

Digital Logic Design using Verilog@HDL

 

34

21.03.2024

Combinational Circuit Design using Verilog@HDL

 (Mux, Demu)

35

22.03.2024

Combinational Circuit Design using Verilog@HDL

 (Decoder, Encoder, ALU)

 

Certificate Course: Module 8

36

25.03.2024

Concept of Bipolar Junction Transistors(BJT): NPN & PNP

37

26.03.2024

NPN & PNP Transistors actions, Input and Output Characteristics of CB Configuration 

38

27.03.2024

NPN & PNP TransistorsInput and Output Characteristics of CE Configuration  & its Applications

 

39

28.03.2024

NPN & PNP Transistors Input and Output Characteristics of CC Configuration  & its Applications

 

40

29.03.2024

NPN & PNP Transistors DC & Load Line Analysis, Operating Points

Certificate Course: Module 9

41

01.04.2024

NPN & PNP Transistors Biasing strategies

42

02.04.2024

NPN & PNP  Fixed Bias, Emitter/Self Bias

43

03.04.2024

NPN & PNP  Low Frequency Response in CE Configuration

44

04.04.2024

Relation between, Alpha, Betta & Gama

45

05.04.2024

Logic Gates Design using NPN & PNP Transistors

Certificate Course: Module 10

46

08.04.2024

Sequential Circuit Design using Verilog@HDL: SR Flip Flop, D Flip Flop

47

09.04.2024

Sequential Circuit Design using Verilog@HDL :T Flip Flop, JK Flip Flop

48

10.04.2024

Sequential Circuit Design using Verilog@HDL:  Master & Slave JK Flip Flop, Ring Counter

49

11.04.2024

Sequential Circuit Design using Verilog@HDL: Asynchronous Counter, Synchronous Counter

50

12.04.2024

Sequential Circuit Design using Verilog@HDL: Registers, Shift Registers

Certificate Course: Module 11

51

15.04.2024

Sequential Circuit Design using VHDL: SR Flip Flop, D Flip Flop

52

16.04.2024

Sequential Circuit Design using VHDL: T Flip Flop, JK Flip Flop

53

17.04.2024

Sequential Circuit Design using VHDL:  Master & Slave JK Flip Flop, Ring Counter

54

18.04.2024

Sequential Circuit Design using VHDL: Asynchronous Counter, Synchronous Counter

55

19.04.2024

Sequential Circuit Design using VHDL: Registers, Shift Registers

Certificate Course: Module 12

56

22.04.2024

Design of Difference Amplifier using BJT

57

23.04.2024

Design of Two Stage Operational Amplifier

58

24.04.2024

Mathematical Analysis of Two stage Operational Amplifier

59

25.04.2024

Characteristics of an Ideal and Practical Operational Amplifier (IC 741)

60

26.04.2024

Inverting and Noninverting Amplifier (using IC741)

Certificate Course: Module 13

61

29.04.2024

Offset Error Voltages & Currents (using IC741)

62

30.04.2024

Power Supply Rejection Ratio (PSRR), Slew Rate & Virtual Ground (using IC741)

63

01.05.2024

Summing & Difference Amplifier (using IC741)

64

02.05.2024

Differentiator & Integrator (using IC741)

65

03.05.2024

 RC Phase Shift Oscillator (using IC741)

Certificate Course: Module 14

66

06.05.2024

Concept of Positive & Negative Feedback

67

07.05.2024

Barkhausen Criterion for Sustained Oscillations

68

08.05.2024

Determination of Frequency and Conditions of Oscillations

69

09.05.2024

RC Phase Shift Oscillator

70

10.05.2024

Hartley & Colpits Oscillator

Certificate Course: Module 15

71

13.05.2024

MOSFET as Switch

72

14.05.2024

MOSFET Structure, MOS Symbols

73

15.05.2024

MOS I/V Characteristics, Threshold Voltage

74

16.05.2024

Derivation of I/V Characteristics

75

17.05.2024

MOS Device Models, MOS Device Layout

Certificate Course: Module 16

76

20.05.2024

MOS Device Capacitances, MOS Small-Signal Model

77

21.05.2024

MOS SPICE models, NMOS versus PMOS Devices

78

22.05.2024

Long-Channel versus Short-Channel Devices

79

23.05.2024

Single Stage Amplifier :Common-Source Stage

80

24.05.2024

Single Stage Amplifier: Common-Source Stage with Resistive Load

Certificate Course: Module 17

81

27.05.2024

Single Stage Amplifier:CS Stage with Diode-Connected Load

82

28.05.2024

Single Stage Amplifier: CS Stage with Current-Source Load

83

29.05.2024

Single Stage Amplifier: Stage with Triode Load

84

30.05.2024

Single Stage Amplifier: CS Stage with Source Degeneration & Source Follower

85

31.05.2024

Single Stage Amplifier: Common-Gate Stage, Cascode Stage, Folded Cascode

Certificate Course: Module 18

86

03.06.2024

Differential Amplifiers: Single-Ended and Differential Operation

87

04.06.2024

Differential Amplifiers: Basic Differential Pair

88

05.06.2024

Differential Amplifiers: Qualitative  and Quantitative Analysis

89

06.06.2024

Differential Amplifiers: Common-Mode Response

90

07.06.2024

Differential Amplifiers: Differential Pair with MOS Loads

Certificate Course: Module 19

91

10.06.2024

 Passive and Active Current Mirrors

92

11.06.2024

Basic Current Mirrors and Cascode Current Mirrors

93

12.06.2024

Active Current Mirrors and Gilbert Cell

94

13.06.2024

Large-Signal  and Small-Signal Analysis

95

14.06.2024

Frequency Response of Amplifiers: Miller Effect

Certificate Course: Module 20

96

17.06.2024

Frequency Response of Amplifiers: Association of Poles with Nodes and Common-Source Stage

 

97

18.06.2024

Frequency Response of Amplifiers: Source Followers and Common-Gate Stage

 

98

19.06.2024

Frequency Response of Amplifiers: Cascode Stage and  Differential Pair Feedback General Considerations

 

99

20.06.2024

Frequency Response of Amplifiers:Properties of Feedback Circuits & Feedback topologies

 

100

21.06.2024

Frequency Response of Amplifiers: Voltage-Voltage Feedback and Current-Voltage Feedback

 

Certificate Course: Module 21

101

24.06.2024

Frequency Response of Amplifiers: Voltage-Current Feedback and Current-Current Feedback

 

102

25.06.2024

Frequency Response of Amplifiers: Effect of Loading and Two-Port Network Models

 

103

26.06.2024

Frequency Response of Amplifiers: Loading in Voltage-Voltage Feedback and Loading in Current-Voltage Feedback

 

104

27.06.2024

Frequency Response of Amplifiers:Loading in Voltage-Current Feedback and Loading in Current-Current Feedback

 

105

28.06.2024

Frequency Response of Amplifiers: Effect of Feedback on Noise

Certificate Course: Module 22

106

01.07.2024

CMOS Operational Amplifiers: Performance Parameters

107

02.07.2024

CMOS Operational Amplifiers: One-Stage Op Amps

108

03.07.2024

CMOS Operational Amplifiers: Two-Stage Op Amps

 

109

04.07.2024

CMOS Operational Amplifiers: Gain Boosting  and Comparison

110

05.07.2024

CMOS Operational Amplifiers: Common-Mode Feedback and Input Range Limitations

 

Certificate Course: Module 23

111

08.07.2024

CMOS Operational Amplifiers: Slew Rate and  Power Supply Rejection

 

112

09.07.2024

CMOS Operational Amplifiers:Stability and Frequency Compensation

 

113

10.07.2024

CMOS Operational Amplifiers: Phase Margin, Frequency Compensation,

 

114

11.07.2024

CMOS Operational Amplifiers:Compensation of Two-Stage Op Amps

 

115

12.07.2024

CMOS Operational Amplifiers: Slewing in Two-Stage Op Amps, Other Compensation Techniques

 

Certificate Course: Module 24

116

15.07.2024

Introduction to Testing: Testing Philosophy

117

16.07.2024

Introduction to Testing: Role of Testing

118

17.07.2024

Introduction to Testing : Digital and Analog VLSI Testing

119

18.07.2024

Introduction to Testing: VLSI Technology Trends Affecting Testing

 

120

19.07.2024

VLSI Testing Process and Test Equipment: How to Test Chips?

Certificate Course: Module 25

121

22.07.2024

VLSI Testing Process and Test Equipment: Automatic Test Equipment

 

122

23.07.2024

VLSI Testing Process and Test Equipment: Electrical Parametric Testing

 

123

24.07.2024

VLSI Testing Process and Test Equipment: Faults in Digital Circuits (Failures and Faults, Modeling of Faults, Temporary Faults)

 

124

25.07.2024

Test Generation for Combinational Logic Circuits: Fault Diagnosis of Digital Circuits

 

125

26.07.2024

Test Generation for Combinational Logic Circuits: Test Generation Techniques for Combinational Circuits

 

Certificate Course: Module 26

126

29.07.2024

Test Generation for Combinational Logic Circuits: Detection of Multiple Faults in Combinational Logic Circuits

 

127

30.07.2024

Test Generation for Combinational Logic Circuits: Testable Combinational Logic Circuit Design

 

128

31.07.2024

Test Generation for Combinational Logic Circuits:The Reed-Mullar Expansion Technique

 

129

01.08.2024

Test Generation for Combinational Logic Circuits: Three-Level OR-AND-OR Design

 

130

02.08.2024

Test Generation for Combinational Logic Circuits: Automatic Synthesis of Testing Logic

 

Certificate Course: Module 27

131

05.08.2024

Test Generation for Combinational Logic Circuits: Testable Design of Multilevel Combinational Circuits

 

132

06.08.2024

Test Generation for Combinational Logic Circuits: Synthesis of Random Pattern Testable Combinational Circuits

 

133

07.08.2024

Test Generation for Combinational Logic Circuits: Path Delay Fault Testable Combinational Logic Design

 

134

08.08.2024

Test Generation for Combinational Logic Circuits: Testable PLA Design

 

135

09.08.2024

Practice Session for fault detection in Combinational Circuits

Certificate Course: Module 28

136

12.08.2024

Test Generation for Sequential Circuits: Testing of Sequential Circuits as Iterative Combinational Circuits

 

137

13.08.2024

Test Generation for Sequential Circuits: State Table Verification

138

14.08.2024

Test Generation for Sequential Circuits: Test Generation Based on Circuit Structure

 

139

15.08.2024

Test Generation for Sequential Circuits: Functional Fault Models

140

16.08.2024

Test Generation for Sequential Circuits: Test Generation Based on Functional Fault Models

 

Certificate Course: Module 29

141

19.08.2024

Design of Testable Sequential Circuits: Controllability and Observability

 

142

20.08.2024

Design of Testable Sequential Circuits: Ad Hoc Design Rules for Improving Testability

 

143

21.08.2024

Design of Testable Sequential Circuits: Design of Dignosable Sequential Circuits

 

144

22.08.2024

Design of Testable Sequential Circuits: The Scan-Path Technique for Testable Sequential Circuit Design

 

145

23.08.2024

Design of Testable Sequential Circuits: Level-Sensitive Scan Design

 

Certificate Course: Module 30

146

26.08.2024

Design of Testable Sequential Circuits: Random Access Scan Technique,

147

27.08.2024

Design of Testable Sequential Circuits:Partial Scan

148

28.08.2024

Design of Testable Sequential Circuits:Testable Sequential Circuit Design Using Nonscan Techniques

 

149

29.08.2024

Design of Testable Sequential Circuits:Cross Check and Boundary Scan

 

150

30.08.2024

Built-In Self-Test: Test Pattern Generation for BIST

Certificate Course: Module 31

151

02.09.2024

Built-In Self-Test: Output Response Analysis

152

03.09.2024

Built-In Self-Test: Circular BIST & BIST Architectures

153

04.09.2024

Testable Memory Design: RAM Fault Models

154

05.09.2024

Testable Memory Design: Test Algorithms for RAMs and Detection of Pattern Sensitive Faults

 

155

06.09.2024

Testable Memory Design: BIST Techniques for RAM Chips and Test Generation and BIST for Embedded RAMS

 

Certificate Course: Module 32

156

09.09.2024

Random Access Memory Technologies: Static Random Access Memories (SRAMs)

 

157

10.09.2024

Random Access Memory Technologies: SRAM Cell Structures and MOS SRAM Architecture

 

158

11.09.2024

Random Access Memory Technologies:MOS SRAM Cell and Peripheral Circuit

 

159

12.09.2024

Random Access Memory Technologies:Bipolar SRAM, SOl and Advanced SRAM Architectures

 

160

13.09.2024

Random Access Memory Technologies:Error Failures in DRAM, Advanced DRAM Design and Architecture, Application of Specific DRAM

Certificate Course: Module 33

161

16.09.2024

Non-Volatile Memories:High Density ROMs and PROMs

162

17.09.2024

Non-Volatile Memories: Bipolar & CMOS PROM

163

18.09.2024

Non-Volatile Memories:EEPROMs and Floating Gate EPROM Cell

164

19.09.2024

Non-Volatile Memories:OTP EPROM and EEPROMs

165

20.09.2024

Non-Volatile Memories:Nonvolatile SRAM and Flash Memories

Certificate Course: Module 34

166

23.09.2024

Semiconductor Memory Reliability and Radiation Effects: General Reliability Issues, RAM Failure Modes and Mechanism

167

24.09.2024

Semiconductor Memory Reliability and Radiation Effects: Nonvolatile Memory, Reliability Modeling and Failure Rate Prediction

168

25.09.2024

Semiconductor Memory Reliability and Radiation Effects: Reliability Screening and Qualification. Radiation Effects

 

169

26.09.2024

Semiconductor Memory Reliability and Radiation Effects: SEP and Radiation Hardening Techniques.

170

27.09.2024

Semiconductor Memory Reliability and Radiation Effects: Process and Design Issues, Radiation Hardened Memory Characteristics and Radiation Hardness Assurance and Testing.

Certificate Course: Module 35

171

30.09.2024

Advanced Memory Technologies and High-density Memory Packing Technologies:: Ferroelectric Random Access Memories (FRAMs), Gallium Arsenide (GaAs) FRAMs

 

172

01.10.2024

Advanced Memory Technologies and High-density Memory Packing Technologies:Analog Memories and Magneto Resistive Random Access Memories (MRAMs)

 

173

02.10.2024

Advanced Memory Technologies and High-density Memory Packing Technologies:Experimental Memory Devices

 

174

03.10.2024

Advanced Memory Technologies and High-density Memory Packing Technologies: Memory Hybrids (2D & 3D), Memory Stacks, Memory Testing and Reliability Issues

 

175

04.10.2024

Advanced Memory Technologies and High-density Memory Packing Technologies:Memory Cards, High Density Memory Packaging, Future Directions, Introduction to digital tablet PC, LCD and DVD player

 

Certificate Course: Module 36

176

07.10.2024

VLSI physical design automation::VLSI Design cycle and New trends in VLSI design

 

177

08.10.2024

VLSI physical design automation: Physical design cycle and Design style

 

178

09.10.2024

VLSI physical design automation: Design rules & layout of basic devices

 

179

10.10.2024

VLSI automation Algorithms Partitioning:Problem formulation, and classification of partitioning algorithms

 

180

11.10.2024

VLSI automation Algorithms Partitioning:Group migration algorithms and simulated annealing

 

Certificate Course: Module 37

181

14.10.2024

Floor planning & pin assignment: Problem formulation and classification of floorplanning algorithms

182

15.10.2024

Floor planning & pin assignment:constraint based floor planning, floor-planning algorithms for mixed black & cell design

183

16.10.2024

Floor planning & pin assignment:chip planning, pin assignment,  and problem formulation

184

17.10.2024

Floor planning & pin assignment:classification of pin assignment algorithms, General & channel pin assignment Placement Problem formulation

185

18.10.2024

Floor planning & pin assignment:, classification of placement algorithms, simulation base placement algorithms and recent trends in placement

Certificate Course: Module 38

186

20.10.2024

Global Routing and Detailed routing:Problem formulation, classification of global routing algorithms and Maze routing algorithm

187

21.10.2024

Global Routing and Detailed routing:line probe algorithm and Steiner Tree based algorithms

188

22.10.2024

Global Routing and Detailed routing:performance driven routing Detailed routing problem formulation and classification of routing algorithms

189

23.10.2024

Global Routing and Detailed routing: introduction to single layer routing algorithms and two layer channel routing algorithms,

190

24.10.2024

Global Routing and Detailed routing:greedy channel routing and switchbox routing algorithms

Certificate Course: Module 39

191

27.10.2024

Over the cell routing & via minimization:Two layers over the cell routers

192

28.10.2024

Over the cell routing & via minimization:constrained & unconstrained via minimization

193

29.10.2024

Compaction:Problem formulation

194

30.10.2024

Compaction:classification of compaction algorithms

195

31.10.2024

Compaction:one dimensional compaction, two dimension based compaction, hierarchical compaction

Certificate Course: Module 40

196

01.11.2024

IC Technology & Fabrication: Wafer Preparation

197

02.11.2024

IC Technology & Fabrication: Oxidation

198

03.11.2024

IC Technology & Fabrication:Photolithography & Etching 

 

199

04.11.2024

IC Technology & Fabrication:Diffusion & Ion Implantation

200

05.11.2024

IC Technology & Fabrication: Metalization

After Registration in the Certificate Course or Internship try to fill the participant information sheet for further quick communications

Link for Participants Information Sheet (Interested participants can register here and hard copy Registration Form  send to isve.cc.chipdesign@gmail.com ):

https://docs.google.com/forms/d/e/1FAIpQLSek2De1C_KAEgf31QDf5L_q4Y6wD-LyX0GQ7Dy7efT_XR7L2g/viewform

Link for Experts: Interested  VLSI Design  expert  can fill their consent here https://docs.google.com/forms/d/e/1FAIpQLSeNIWWkKuOlMoZYB3PRDBLp5SAbZ7OKZmiy4rLgbAVrREpHQA/viewform

For any queries and support write mail to us at isve.cc.chipdesign@gmail.com  or contact the General Chair (9973886214).

 

List of Resource Persons for Certificate Course on Chip Design & FPGA System Design (CDFD-2024): https://docs.google.com/document/d/1ehX93CLH8I6ggqqJUW4rmU21Rdy4UMzWzARM0AnYSEY/edit 

 

Thanks & regards
 
Organizing Committee
Certificate Course on Chip Design & FPGA System Design (CDFD-2024)/ Faculty Development Program on Chip Designing / Internship on VLSI Design
organized by Indian Society for VLSI Education(ISVE) Ranchi under aegis of India Semiconductor Mission(ISM) in Online Mode/ Virtual Mode
 
 
 
 
 
 

B. GLIPMS OF PREVIOUS WORKSHOPS/ SHORT TERM COURSES

1.     Summer School on Digital VLSI Design(SSDVD_2014)from June 16-30,2014 in three phases, Organized by Indian Society for VLSI Education & IETE, Ranchi Centre at ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India. 

2.   Winter School on Digital VLSI Design(WSDVD_2014)from Dec 16-30,2014 in three phases, Organized by Indian Society for VLSI Education & IETE, Ranchi Centre at ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India http://ieteranchi.org/images/wsdvd_2014.pdf

3.    Summer  School on Digital VLSI Design(SSDVD_2015)from June 16-30,2015 in three phases, Organized by Indian Society for VLSI Education & IETE, Ranchi Centre at ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India.  http://www.ieteranchi.org/images/pdf/brochure_SSDVD_2015.pdf

4.    Winter School on Digital VLSI Design(WSDVD_2015)from Dec 16-30,2015 in three phases, Organized by Indian Society for VLSI Education, Ranchi Centre at ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India. http://www.isve.in/Default?page=adminisve&pid=WSDVD-2015

5.   Winter School on Digital VLSI Design(WSDVD_2016)from Dec 27-31,2016  Organized by Indian Society for VLSI Education, Ranchi & IETE Ranchi Centre at ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India. http://www.isve.in/Default?page=adminisve&pid=WSDVD-2016

6.   Summer School on Digital VLSI Design(SSDVD_2017)from June 21-30,2017 in two phases, Organized by Indian Society for VLSI Education & IETE, Ranchi Centre at ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India. http://www.isve.in/Default?page=adminisve&pid=SSDVD-2017

7.  Winter School on Digital VLSI Design(WSDVD_2017)from Dec 21-30,2017 in two phases, Organized by Indian Society for VLSI Education & IETE, Ranchi Centre at ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India.

8.   Summer School on Digital VLSI Design(SSDVD_2018)from June 1-30,2018 in two phases, Organized by Indian Society for VLSI Education & IETE, Ranchi Centre at ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India. http://www.isve.in/Default?page=adminisve&pid=SSDVD-2018

9.   Winter School on Digital VLSI Design(WSDVD_2018)from Dec 26-30,2018 in two phases, Organized by Indian Society for VLSI Education & IETE, Ranchi Centre at ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India, http://www.isve.in/Default?page=adminisve&pid=WSDVD-2018

10.  Summer School on Digital VLSI Design(SSDVD_2019)& 1st International Science Exhibition Congress(SEC-2019)from June 26-30,2019 in one phase, Organized by Indian Society for VLSI Education & IETE, Ranchi Centre at ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India, www.isve.in/Default?page=adminisve&pid=SSDVD-SEC-201

11.  Summer School on Digital VLSI Design(SSDVD_2020) & 3rd International Science Exhibition Congress(SCE-2020) from June 26-30,2020 in one phase, Organized by Indian Society for VLSI Education & IETE, Ranchi Centre at ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India, http://www.isve.in/Default?page=adminisve&pid=SSDVD-SEC-2020