INDIAN SOCIETY FOR VLSI EDUCATION, RANCHI

ISVE Certificate Course on Chip Design

Certificate Course on Chip Design & FPGA System Design (CDFD-2024)

Dear Sir/Madam,

We are pleased to share that Indian Society for VLSI Education(ISVE) Ranchi is organizing Certificate Course on Chip Design & FPGA System Design(CDFD-2024) /Faculty Development Program on Chip Designing / Internship on VLSI Design under ages of India Semiconductor Mission(ISM)  from 5th Feb 2023 to 5th Dec 2024 in Virtual Mode(Online Mode) for preparing the trained manpower in VLSI Design & Embedded Systems  with following Academic Universities, Institutions and Industries: 

SNName of Universities/ Institutions/IndustriesName of Coordinators/ Co-Organizers
1.School of Studies in Electronics & Photonics & Institute of Renewable Energy Technology & ManagementPt. Ravishankar Shukla University Raipur (CG)Dr. Kavita ThakurProfessor & Head
2.Department of ElectronicsShri. Shivaji Vidyaprasarak Sanstha’sBapusaheb Shivajirao Deore College of Engineering, Dhule.Dr. Sagar A. MoreAssociate Professor 
3.  
4.  
   

There are huge demand of trends power in this area. Number of core companies, startups and Educational Institutions are seeking the trained manpower in this domain.

Lecture will be delivered by subject experts from Industry and Academia. Classes will be from 6:00pm to 7:30pm (Monday to Friday).  It will cover theory with practical. 

Courses are offered module wise by Monday to Friday, some special classes will be offered Saturday or Sunday as per needs. Interested participants can register module wise, attend the lecture and do the practice on the related software. Job Guarantees  who will be completed all modules successfully.

Benefits to the Institutional Membership/ Student Chapters/ MoU with ISVE: A Institute who have Institutional Membership / Student Chapters/ MoU with ISVE Ranchi will get the 10% discount in their students /faculties fees.

Honorarium to Course Expert:

A faculty/ Scientist / Engineers who are involved in Certificate Course on Chip Design & FPGA System Design(CDFD-2024) / Faculty Development Program of Chip Designing / Internship on VLSI Design

will get the honorarium as per ISVE Rules. A person have abilities to teach the students at current job level can fill their consent in google sheet. Organizing committee will contact you for the same.

A list of VLSI Core Companies who are offering the Job in VLSI Design:

A list of companies and startups are seeking trained manpower for core VLSI Design work.

  1. https://www.naukri.com/vlsi-jobs
  2. https://in.linkedin.com/jobs/vlsi-design-jobs 
  3. https://in.linkedin.com/jobs/vlsi-jobs 
  4. https://www.maven-silicon.com/vlsi-jobs-for-freshers/ 
  5. https://www.glassdoor.co.in/Job/india-vlsi-design-jobs-SRCH_IL.0,5_IN115_KO6,17.htm
  6. https://www.rv-skills.com/career-opportunities-in-VLSI.php 

There are very good future of this area. 

About ISVE Ranchi : It is non profitable registered society dedicated to serve the nation. It makes a bridge between industry and academia for organizing the workshops, summer/winter schools, short term courses, conferences, symposiums and seminars by which students, research scholars, faculties and scientists come together, work together and share their knowledge in recent development in engineering, science & technology[www.isve.in]. 

 Registration:  Registration Form

1.      Registration fee includes conference kit & study materials. Participants have a special provision to select their training/ internship module wise. Now, Registration is open for all modules. Interested can select the module and register.

2.      Please download the Registration Form from the mail-attachment/website and send scan copy of filled Registration Form with NEFT receipt through e-mail for early registration. A/C Name: INDIAN SOCIETY FOR VLSI EDUCATION, A/C Number: 01670110061831, IFSC Code: UCBA0000167, Bank: UCO Bank, Branch: Mesra Ranchi, Address: BIT Main Building Mesra, Dist: Ranchi, State: Jharkhand, Contact No: 0651-2275829.

Certificate Course on Chip Design and FPGA System Design (CDFD-2024) / Faculty Development Program on Chip Designing /Internship on VLSI DesignProgram Schedule & Fees Details
SNTraining ScheduleCategory of Candidate & FeesUG/PG/PhDIndian RsCategory of Candidate & FeesEngineer/Faculty/ScientistIndian Rs
1.5 days20004000
2.10 days40008000
3.15 days600012000
4.20 days800016000
5.25 days1000020000
6.30 days1200024000
7.35 days1400028000
8.40 days1600032000
9.45 days1800036000
10.50 days2000040000
11.55 days2200044000
1260 days2400048000
1365 days2600052000
1470 days2800056000
1575 days3000060000
1680 days3200064000
1785 days3400068000
1890 days3600072000
1995 days3800076000
20100 days4000080000
21105 days4200084000
22110 days4400088000
23115 days4600092000
24120 days4800096000
25125 days50000100000
26130 days52000104000
27135 days54000108000
28140 days56000112000
29145 days58000116000
30150 days60000120000
31155 days62000124000
32160 days64000128000
33165 days66000132000
34170 days68000136000
35175 days70000140000
36180 days72000144000
37185 days74000148000
38190 days76000152000
39195 days78000156000
40200 days80000160000
    

Course Syllabus: Attachment

Syllabus of Certificate Course of Chip Design & FPGA System Design (CDFD-2024)/ Faculty Development Program on Chip Designing/ Internship on VLSI Design

5 days to 200 days courses are available here for Certificate Course , Faculty Development Program and Internship here:

https://docs.google.com/document/d/1ZMxY9SHpu14qgPJV4ddrqjO_ZhJaIo-Q/edit?pli=1
SNScheduled DateCourse Contents
           Certificate Course: Module 1
105.02.2024Fundamentals of Chip Design
206.02.2024Fundamentals of IC technologies
307.02.2024Fundamentals of logic design
408.02.2024Fundamentals of VHDL and Verilog
509.02.2024Fundamentals of FPGA System Design
Certificate Course: Module 2
612.02.2024Fundamentals of PN junction diode
713.02.2024Design & Functionality of PN junction diode
814.02.2024Fundamentals of MOSFET
915.02.2024Design of MOSFET
1016.02.2024Functionality of MOSFET & its Characteristics
Certificate Course: Module 3
1119.02.2024PN Junction Diode as Half Wave Rectifier, Full Wave Rectifier (Bridge Rectifier, Centre Tapped Rectifier)
1220.02.2024Design of Zener Diode
1321.02.2024Application of Zener Diode as Regulator
1422.02.2024Design of JFET
1523.02.2024Functionality of JFET and its Characteristics
Certificate Course: Module 4
1626.02.2024Logic Gates Design using MOSFET
1727.02.2024Combinational Circuit Design using MOSFET (Mux, Demux)
1828.02.2024Combinational Circuit Design using MOSFET (Decoder, Encoder, ALU)
1929.02.2024Sequential Circuit Design using MOSFET (Flip-Flops)
2001.03.2024Sequential Circuit Design using MOSFET (Registers, Counters)
Certificate Course: Module 5
2104.03.2024Introduction to Boolean Algebra
2205.03.2024Introduction to Boolean Operators
2306.03.2024Symbolic Representation, Boolean Algebraic Function & Truth Table of Different Logic Gates
2407.03.2024Circuit Optimization Techniques by Boolean Axioms & K-Map
2508.03.2024Design of Basic Gates using Universal Gates
Certificate Course: Module 6
2611.03.2024Introduction of VHDL
2712.03.2024Important Terms of VHDL
2813.03.2024Digital Logic Design using VHDL
2914.03.2024Combinational Circuit Design using VHDL (Mux, Demu)
3015.03.2024Combinational Circuit Design using VHDL (Decoder, Encoder, ALU)
Certificate Course: Module 7
3118.03.2024Introduction to Verilog
3219.03.2024Programing of Verilog@HDL
3320.03.2024Digital Logic Design using Verilog@HDL 
3421.03.2024Combinational Circuit Design using Verilog@HDL (Mux, Demu)
3522.03.2024Combinational Circuit Design using Verilog@HDL (Decoder, Encoder, ALU)
 Certificate Course: Module 8
3625.03.2024Concept of Bipolar Junction Transistors(BJT): NPN & PNP
3726.03.2024NPN & PNP Transistors actions, Input and Output Characteristics of CB Configuration 
3827.03.2024NPN & PNP TransistorsInput and Output Characteristics of CE Configuration  & its Applications 
3928.03.2024NPN & PNP Transistors Input and Output Characteristics of CC Configuration  & its Applications 
4029.03.2024NPN & PNP Transistors DC & Load Line Analysis, Operating Points
Certificate Course: Module 9
4101.04.2024NPN & PNP Transistors Biasing strategies
4202.04.2024NPN & PNP  Fixed Bias, Emitter/Self Bias
4303.04.2024NPN & PNP  Low Frequency Response in CE Configuration
4404.04.2024Relation between, Alpha, Betta & Gama
4505.04.2024Logic Gates Design using NPN & PNP Transistors
Certificate Course: Module 10
4608.04.2024Sequential Circuit Design using Verilog@HDL: SR Flip Flop, D Flip Flop
4709.04.2024Sequential Circuit Design using Verilog@HDL :T Flip Flop, JK Flip Flop
4810.04.2024Sequential Circuit Design using Verilog@HDL:  Master & Slave JK Flip Flop, Ring Counter
4911.04.2024Sequential Circuit Design using Verilog@HDL: Asynchronous Counter, Synchronous Counter
5012.04.2024Sequential Circuit Design using Verilog@HDL: Registers, Shift Registers
Certificate Course: Module 11
5115.04.2024Sequential Circuit Design using VHDL: SR Flip Flop, D Flip Flop
5216.04.2024Sequential Circuit Design using VHDL: T Flip Flop, JK Flip Flop
5317.04.2024Sequential Circuit Design using VHDL:  Master & Slave JK Flip Flop, Ring Counter
5418.04.2024Sequential Circuit Design using VHDL: Asynchronous Counter, Synchronous Counter
5519.04.2024Sequential Circuit Design using VHDL: Registers, Shift Registers
Certificate Course: Module 12
5622.04.2024Design of Difference Amplifier using BJT
5723.04.2024Design of Two Stage Operational Amplifier
5824.04.2024Mathematical Analysis of Two stage Operational Amplifier
5925.04.2024Characteristics of an Ideal and Practical Operational Amplifier (IC 741)
6026.04.2024Inverting and Noninverting Amplifier (using IC741)
Certificate Course: Module 13
6129.04.2024Offset Error Voltages & Currents (using IC741)
6230.04.2024Power Supply Rejection Ratio (PSRR), Slew Rate & Virtual Ground (using IC741)
6301.05.2024Summing & Difference Amplifier (using IC741)
6402.05.2024Differentiator & Integrator (using IC741)
6503.05.2024 RC Phase Shift Oscillator (using IC741)
Certificate Course: Module 14
6606.05.2024Concept of Positive & Negative Feedback
6707.05.2024Barkhausen Criterion for Sustained Oscillations
6808.05.2024Determination of Frequency and Conditions of Oscillations
6909.05.2024RC Phase Shift Oscillator
7010.05.2024Hartley & Colpits Oscillator
Certificate Course: Module 15
7113.05.2024MOSFET as Switch
7214.05.2024MOSFET Structure, MOS Symbols
7315.05.2024MOS I/V Characteristics, Threshold Voltage
7416.05.2024Derivation of I/V Characteristics
7517.05.2024MOS Device Models, MOS Device Layout
Certificate Course: Module 16
7620.05.2024MOS Device Capacitances, MOS Small-Signal Model
7721.05.2024MOS SPICE models, NMOS versus PMOS Devices
7822.05.2024Long-Channel versus Short-Channel Devices
7923.05.2024Single Stage Amplifier :Common-Source Stage
8024.05.2024Single Stage Amplifier: Common-Source Stage with Resistive Load
Certificate Course: Module 17
8127.05.2024Single Stage Amplifier:CS Stage with Diode-Connected Load
8228.05.2024Single Stage Amplifier: CS Stage with Current-Source Load
8329.05.2024Single Stage Amplifier: Stage with Triode Load
8430.05.2024Single Stage Amplifier: CS Stage with Source Degeneration & Source Follower
8531.05.2024Single Stage Amplifier: Common-Gate Stage, Cascode Stage, Folded Cascode
Certificate Course: Module 18
8603.06.2024Differential Amplifiers: Single-Ended and Differential Operation
8704.06.2024Differential Amplifiers: Basic Differential Pair
8805.06.2024Differential Amplifiers: Qualitative  and Quantitative Analysis
8906.06.2024Differential Amplifiers: Common-Mode Response
9007.06.2024Differential Amplifiers: Differential Pair with MOS Loads
Certificate Course: Module 19
9110.06.2024 Passive and Active Current Mirrors
9211.06.2024Basic Current Mirrors and Cascode Current Mirrors
9312.06.2024Active Current Mirrors and Gilbert Cell
9413.06.2024Large-Signal  and Small-Signal Analysis
9514.06.2024Frequency Response of Amplifiers: Miller Effect
Certificate Course: Module 20
9617.06.2024Frequency Response of Amplifiers: Association of Poles with Nodes and Common-Source Stage 
9718.06.2024Frequency Response of Amplifiers: Source Followers and Common-Gate Stage 
9819.06.2024Frequency Response of Amplifiers: Cascode Stage and  Differential Pair Feedback General Considerations 
9920.06.2024Frequency Response of Amplifiers:Properties of Feedback Circuits & Feedback topologies 
10021.06.2024Frequency Response of Amplifiers: Voltage-Voltage Feedback and Current-Voltage Feedback 
Certificate Course: Module 21
10124.06.2024Frequency Response of Amplifiers: Voltage-Current Feedback and Current-Current Feedback 
10225.06.2024Frequency Response of Amplifiers: Effect of Loading and Two-Port Network Models 
10326.06.2024Frequency Response of Amplifiers: Loading in Voltage-Voltage Feedback and Loading in Current-Voltage Feedback 
10427.06.2024Frequency Response of Amplifiers:Loading in Voltage-Current Feedback and Loading in Current-Current Feedback 
10528.06.2024Frequency Response of Amplifiers: Effect of Feedback on Noise
Certificate Course: Module 22
10601.07.2024CMOS Operational Amplifiers: Performance Parameters
10702.07.2024CMOS Operational Amplifiers: One-Stage Op Amps
10803.07.2024CMOS Operational Amplifiers: Two-Stage Op Amps 
10904.07.2024CMOS Operational Amplifiers: Gain Boosting  and Comparison
11005.07.2024CMOS Operational Amplifiers: Common-Mode Feedback and Input Range Limitations 
Certificate Course: Module 23
11108.07.2024CMOS Operational Amplifiers: Slew Rate and  Power Supply Rejection 
11209.07.2024CMOS Operational Amplifiers:Stability and Frequency Compensation 
11310.07.2024CMOS Operational Amplifiers: Phase Margin, Frequency Compensation, 
11411.07.2024CMOS Operational Amplifiers:Compensation of Two-Stage Op Amps 
11512.07.2024CMOS Operational Amplifiers: Slewing in Two-Stage Op Amps, Other Compensation Techniques 
Certificate Course: Module 24
11615.07.2024Introduction to Testing: Testing Philosophy
11716.07.2024Introduction to Testing: Role of Testing
11817.07.2024Introduction to Testing : Digital and Analog VLSI Testing
11918.07.2024Introduction to Testing: VLSI Technology Trends Affecting Testing 
12019.07.2024VLSI Testing Process and Test Equipment: How to Test Chips?
Certificate Course: Module 25
12122.07.2024VLSI Testing Process and Test Equipment: Automatic Test Equipment 
12223.07.2024VLSI Testing Process and Test Equipment: Electrical Parametric Testing 
12324.07.2024VLSI Testing Process and Test Equipment: Faults in Digital Circuits (Failures and Faults, Modeling of Faults, Temporary Faults) 
12425.07.2024Test Generation for Combinational Logic Circuits: Fault Diagnosis of Digital Circuits 
12526.07.2024Test Generation for Combinational Logic Circuits: Test Generation Techniques for Combinational Circuits 
Certificate Course: Module 26
12629.07.2024Test Generation for Combinational Logic Circuits: Detection of Multiple Faults in Combinational Logic Circuits 
12730.07.2024Test Generation for Combinational Logic Circuits: Testable Combinational Logic Circuit Design 
12831.07.2024Test Generation for Combinational Logic Circuits:The Reed-Mullar Expansion Technique 
12901.08.2024Test Generation for Combinational Logic Circuits: Three-Level OR-AND-OR Design 
13002.08.2024Test Generation for Combinational Logic Circuits: Automatic Synthesis of Testing Logic 
Certificate Course: Module 27
13105.08.2024Test Generation for Combinational Logic Circuits: Testable Design of Multilevel Combinational Circuits 
13206.08.2024Test Generation for Combinational Logic Circuits: Synthesis of Random Pattern Testable Combinational Circuits 
13307.08.2024Test Generation for Combinational Logic Circuits: Path Delay Fault Testable Combinational Logic Design 
13408.08.2024Test Generation for Combinational Logic Circuits: Testable PLA Design 
13509.08.2024Practice Session for fault detection in Combinational Circuits
Certificate Course: Module 28
13612.08.2024Test Generation for Sequential Circuits: Testing of Sequential Circuits as Iterative Combinational Circuits 
13713.08.2024Test Generation for Sequential Circuits: State Table Verification
13814.08.2024Test Generation for Sequential Circuits: Test Generation Based on Circuit Structure 
13915.08.2024Test Generation for Sequential Circuits: Functional Fault Models
14016.08.2024Test Generation for Sequential Circuits: Test Generation Based on Functional Fault Models 
Certificate Course: Module 29
14119.08.2024Design of Testable Sequential Circuits: Controllability and Observability 
14220.08.2024Design of Testable Sequential Circuits: Ad Hoc Design Rules for Improving Testability 
14321.08.2024Design of Testable Sequential Circuits: Design of Dignosable Sequential Circuits 
14422.08.2024Design of Testable Sequential Circuits: The Scan-Path Technique for Testable Sequential Circuit Design 
14523.08.2024Design of Testable Sequential Circuits: Level-Sensitive Scan Design 
Certificate Course: Module 30
14626.08.2024Design of Testable Sequential Circuits: Random Access Scan Technique,
14727.08.2024Design of Testable Sequential Circuits:Partial Scan
14828.08.2024Design of Testable Sequential Circuits:Testable Sequential Circuit Design Using Nonscan Techniques 
14929.08.2024Design of Testable Sequential Circuits:Cross Check and Boundary Scan 
15030.08.2024Built-In Self-Test: Test Pattern Generation for BIST
Certificate Course: Module 31
15102.09.2024Built-In Self-Test: Output Response Analysis
15203.09.2024Built-In Self-Test: Circular BIST & BIST Architectures
15304.09.2024Testable Memory Design: RAM Fault Models
15405.09.2024Testable Memory Design: Test Algorithms for RAMs and Detection of Pattern Sensitive Faults 
15506.09.2024Testable Memory Design: BIST Techniques for RAM Chips and Test Generation and BIST for Embedded RAMS 
Certificate Course: Module 32
15609.09.2024Random Access Memory Technologies: Static Random Access Memories (SRAMs) 
15710.09.2024Random Access Memory Technologies: SRAM Cell Structures and MOS SRAM Architecture 
15811.09.2024Random Access Memory Technologies:MOS SRAM Cell and Peripheral Circuit 
15912.09.2024Random Access Memory Technologies:Bipolar SRAM, SOl and Advanced SRAM Architectures 
16013.09.2024Random Access Memory Technologies:Error Failures in DRAM, Advanced DRAM Design and Architecture, Application of Specific DRAM
Certificate Course: Module 33
16116.09.2024Non-Volatile Memories:High Density ROMs and PROMs
16217.09.2024Non-Volatile Memories: Bipolar & CMOS PROM
16318.09.2024Non-Volatile Memories:EEPROMs and Floating Gate EPROM Cell
16419.09.2024Non-Volatile Memories:OTP EPROM and EEPROMs
16520.09.2024Non-Volatile Memories:Nonvolatile SRAM and Flash Memories
Certificate Course: Module 34
16623.09.2024Semiconductor Memory Reliability and Radiation Effects: General Reliability Issues, RAM Failure Modes and Mechanism
16724.09.2024Semiconductor Memory Reliability and Radiation Effects: Nonvolatile Memory, Reliability Modeling and Failure Rate Prediction
16825.09.2024Semiconductor Memory Reliability and Radiation Effects: Reliability Screening and Qualification. Radiation Effects 
16926.09.2024Semiconductor Memory Reliability and Radiation Effects: SEP and Radiation Hardening Techniques.
17027.09.2024Semiconductor Memory Reliability and Radiation Effects: Process and Design Issues, Radiation Hardened Memory Characteristics and Radiation Hardness Assurance and Testing.
Certificate Course: Module 35
17130.09.2024Advanced Memory Technologies and High-density Memory Packing Technologies:: Ferroelectric Random Access Memories (FRAMs), Gallium Arsenide (GaAs) FRAMs 
17201.10.2024Advanced Memory Technologies and High-density Memory Packing Technologies:Analog Memories and Magneto Resistive Random Access Memories (MRAMs) 
17302.10.2024Advanced Memory Technologies and High-density Memory Packing Technologies:Experimental Memory Devices 
17403.10.2024Advanced Memory Technologies and High-density Memory Packing Technologies: Memory Hybrids (2D & 3D), Memory Stacks, Memory Testing and Reliability Issues 
17504.10.2024Advanced Memory Technologies and High-density Memory Packing Technologies:Memory Cards, High Density Memory Packaging, Future Directions, Introduction to digital tablet PC, LCD and DVD player 
Certificate Course: Module 36
17607.10.2024VLSI physical design automation::VLSI Design cycle and New trends in VLSI design 
17708.10.2024VLSI physical design automation: Physical design cycle and Design style 
17809.10.2024VLSI physical design automation: Design rules & layout of basic devices 
17910.10.2024VLSI automation Algorithms Partitioning:Problem formulation, and classification of partitioning algorithms 
18011.10.2024VLSI automation Algorithms Partitioning:Group migration algorithms and simulated annealing 
Certificate Course: Module 37
18114.10.2024Floor planning & pin assignment: Problem formulation and classification of floorplanning algorithms
18215.10.2024Floor planning & pin assignment:constraint based floor planning, floor-planning algorithms for mixed black & cell design
18316.10.2024Floor planning & pin assignment:chip planning, pin assignment,  and problem formulation
18417.10.2024Floor planning & pin assignment:classification of pin assignment algorithms, General & channel pin assignment Placement Problem formulation
18518.10.2024Floor planning & pin assignment:, classification of placement algorithms, simulation base placement algorithms and recent trends in placement
Certificate Course: Module 38
18620.10.2024Global Routing and Detailed routing:Problem formulation, classification of global routing algorithms and Maze routing algorithm
18721.10.2024Global Routing and Detailed routing:line probe algorithm and Steiner Tree based algorithms
18822.10.2024Global Routing and Detailed routing:performance driven routing Detailed routing problem formulation and classification of routing algorithms
18923.10.2024Global Routing and Detailed routing: introduction to single layer routing algorithms and two layer channel routing algorithms,
19024.10.2024Global Routing and Detailed routing:greedy channel routing and switchbox routing algorithms
Certificate Course: Module 39
19127.10.2024Over the cell routing & via minimization:Two layers over the cell routers
19228.10.2024Over the cell routing & via minimization:constrained & unconstrained via minimization
19329.10.2024Compaction:Problem formulation
19430.10.2024Compaction:classification of compaction algorithms
19531.10.2024Compaction:one dimensional compaction, two dimension based compaction, hierarchical compaction
Certificate Course: Module 40
19601.11.2024IC Technology & Fabrication: Wafer Preparation
19702.11.2024IC Technology & Fabrication: Oxidation
19803.11.2024IC Technology & Fabrication:Photolithography & Etching  
19904.11.2024IC Technology & Fabrication:Diffusion & Ion Implantation
20005.11.2024IC Technology & Fabrication: Metalization

After Registration in the Certificate Course or Internship try to fill the participant information sheet for further quick communications

Link for Participants Information Sheet (Interested participants can register here and hard copy Registration Form  send to isve.cc.chipdesign@gmail.com ):

https://docs.google.com/forms/d/e/1FAIpQLSek2De1C_KAEgf31QDf5L_q4Y6wD-LyX0GQ7Dy7efT_XR7L2g/viewform

Link for Experts: Interested  VLSI Design  expert  can fill their consent here https://docs.google.com/forms/d/e/1FAIpQLSeNIWWkKuOlMoZYB3PRDBLp5SAbZ7OKZmiy4rLgbAVrREpHQA/viewform

For any queries and support write mail to us at isve.cc.chipdesign@gmail.com  or contact the General Chair (9973886214).

List of Resource Persons for Certificate Course on Chip Design & FPGA System Design (CDFD-2024): https://docs.google.com/document/d/1ehX93CLH8I6ggqqJUW4rmU21Rdy4UMzWzARM0AnYSEY/edit 

Thanks & regards

Organizing Committee

Certificate Course on Chip Design & FPGA System Design (CDFD-2024)/ Faculty Development Program on Chip Designing / Internship on VLSI Design

organized by Indian Society for VLSI Education(ISVE) Ranchi under aegis of India Semiconductor Mission(ISM) in Online Mode/ Virtual Mode

B. GLIPMS OF PREVIOUS WORKSHOPS/ SHORT TERM COURSES

1.     Summer School on Digital VLSI Design(SSDVD_2014)from June 16-30,2014 in three phases, Organized by Indian Society for VLSI Education & IETE, Ranchi Centreat ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India. 

2.   Winter School on Digital VLSI Design(WSDVD_2014)from Dec 16-30,2014 in three phases, Organized byIndian Society for VLSI Education & IETE, Ranchi Centre at ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India http://ieteranchi.org/images/wsdvd_2014.pdf

3.    Summer  School on Digital VLSI Design(SSDVD_2015)from June 16-30,2015 in three phases, Organized by Indian Society for VLSI Education & IETE, Ranchi Centreat ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India.  http://www.ieteranchi.org/images/pdf/brochure_SSDVD_2015.pdf

4.    Winter School on Digital VLSI Design(WSDVD_2015)from Dec 16-30,2015 in three phases, Organized by Indian Society for VLSI Education, Ranchi Centreat ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India. http://www.isve.in/Default?page=adminisve&pid=WSDVD-2015

5.   Winter School on Digital VLSI Design(WSDVD_2016)from Dec 27-31,2016  Organized by Indian Society for VLSI Education, Ranchi & IETE Ranchi Centreat ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India. http://www.isve.in/Default?page=adminisve&pid=WSDVD-2016

6.   Summer School on Digital VLSI Design(SSDVD_2017)from June 21-30,2017 in two phases, Organized by Indian Society for VLSI Education & IETE, Ranchi Centreat ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India. http://www.isve.in/Default?page=adminisve&pid=SSDVD-2017

7.  Winter School on Digital VLSI Design(WSDVD_2017)from Dec 21-30,2017 in two phases, Organized by Indian Society for VLSI Education & IETE, Ranchi Centreat ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India.

8.   Summer School on Digital VLSI Design(SSDVD_2018)from June 1-30,2018 in two phases, Organized by Indian Society for VLSI Education & IETE, Ranchi Centreat ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India. http://www.isve.in/Default?page=adminisve&pid=SSDVD-2018

9.   Winter School on Digital VLSI Design(WSDVD_2018)from Dec 26-30,2018 in two phases, Organized by Indian Society for VLSI Education & IETE, Ranchi Centreat ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India, http://www.isve.in/Default?page=adminisve&pid=WSDVD-2018

10.  Summer School on Digital VLSI Design(SSDVD_2019)& 1st International Science Exhibition Congress(SEC-2019)from June 26-30,2019 in one phase, Organized by Indian Society for VLSI Education & IETE, Ranchi Centreat ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India, www.isve.in/Default?page=adminisve&pid=SSDVD-SEC-201

11.  Summer School on Digital VLSI Design(SSDVD_2020) & 3rd International Science Exhibition Congress(SCE-2020) from June 26-30,2020 in one phase, Organized by Indian Society for VLSI Education & IETE, Ranchi Centreat ARTTC, BSNL Near Jumar River, Hazaribag Road, Ranchi, Jharkhand, India, http://www.isve.in/Default?page=adminisve&pid=SSDVD-SEC-2020