Upcoming ISVE Events:
1. 5th International Conference on NMIC-2025 with 10th International Conference NCCS-2024 and 2nd International Conference MSME-2024 will be held on 27-28th April 2024.
Upcoming ISVE Collaborative Events:
1.. Faculty Development Program “Startup in VLSI Design, Embedded System and Computational Intelligence” from 17th January 2025 to 22nd January 2025, Organized by
School of Studies in Electronics and Photonics & Institute Innovation Council
Pt. Ravishankar Shukla University Raipur
&
Indian Society for VLSI Education (ISVE) Ranchi
In collaboration with
Electronics and Information and Communication Technology Academy (E&ICT) of Indian Institute of Communication Technology, Design and Manu-facturing (IIITDM) Jabalpur
2.AICTE SPONSORED
National Summit on VLSI for Smart Signal Processing: The AI & Edge Revolution
(NV-SIGPROC: AI & Edge)
(May 23rd& 24th, 2025)
in association with
Indian Society for VLSI Education (ISVE)
&
The Institution of Electronics and Telecommunication Engineers
Completed Events:
A brief report on Winter School on Digital System Design with Verilog (WS-DSDV-2024) : 26-30th Dec 2024
We are pleased to share that Indian Society for VLSI Education(ISVE) Ranchi with collaborative institutions: Pt Ravi Shankar Shukla University Raipur, Dr DY Patil University Pune, Matrusri Engineering College Hyderbad, Chaitanya Bharati Institute of Technology Hyderabad, Shah & Anchor Kutchhi Engineering College Pune, Bapusaheb Shivajirao Deore College of Engineering Dhule, AISSMS Institute of Information Technology Pune, Dr Vijay Nath Educational Welfare Society Gorakhpur are offering Winter School on Digital System Design with Verilog for UG, PG, PhD Students & industry professionals from 26-30th Dec 2024 in Online Mode. Program was inaugurated by Chief Guest Prof. R.P. Yadav, Former Vice-Chancellor Rajasthan Technological University Kota & HAG Professor MNIT Jaipur.
Dr. Anand Kumar Thakur, Organizing Secretary welcomed to the participants and guest members available on virtual dais. Dr. Vijay Nath, resource person of the program demonstrated the technical advantages and market value of Digital System Design and Verilog coding. Readiness level of students is highly need to startup and upcoming and running industries. Verilog is HDL (Hardware Description Language) used to model the electronic circuits and systems. It is most used in the design and verification of digital circuits at the register -transfer level of the abstractions. It is the most demanding course in the electronics industry.
More than 28 participants were participated across the country. Experts from Academia and industry have delivered their lectures, theory with practical demo such as Dr. Vijay Nath, Associate Professor BIT Mesra; Dr. Adesh Kumar, Professor UPES University Dehradun; Dr. Khaleelu Rhman, Associate Professor CBIT Hyderabad; Sh. Shreyakumar Patel, Sr. Software Engineer NetScout Systems Inc, IEEE,Anna, Texas, USA (Coordinator ISVE Ranchi Chapter, Texas, USA) & Resource Person WS-DSDV-2024.
In this ISVE collaborative program following designated members were invited from collaborative institutions on the virtual dais for knowing the advantage of student’s skill development program and motivation to students in India Semiconductor Mission.
- Dr. D.K. Yadav, Professor & Head, Department of CSE, NIT Jamshedpur & President ISVE Ranchi
- Dr. R.P. Yadav, Professor (HAG) MNIT Jaipur & Former VC Rajasthan Technological University Kota & Brand Ambassador ISVE Ranchi (Chief Guest 1)
- Dr. Kavita Thakur, Professor & Head, SoS in Electronics & Photonics, Pt Ravishankar Shukla University Raipur & Coordinator WS-DSDV-2024 (Chief Guest 2)
- Sh. K.K. Thakur, Former CGMT, Jharkhand Circle, Ranchi & Brand Ambassador ISVE Ranchi (Guest of Honor)
- Dr. N. Srinivasa Rao, Professor & Head, Dept of ECE, MEC, Hyderabad & ISVE Zonal Coordinator, Hyderabad
- Dr. Vijay Nath, Associate Professor, Birla Institute of Technology, Ranchi & Resource Person WS-DSDV-2024
- Dr. Arun Kumar, Former Director ECOM, University Department of Physics, Ranchi University Ranchi & Chairman ISVE Ranchi
- Dr. Anand Kr. Thakur, Assistant Professor, Ranchi University Ranchi & Organizing Secretary WS-DSDV-2024
- Dr. Sagar A. More, Associate Professor Department of Electronics, Bapusaheb Shivajirao Deore College of Engineering, Dhule, Maharashtra
- Dr. Raj Kumar Singh, Assistant Professor, University Department of Physics, Ranchi University Ranchi & Convener WS-DSDV-2024
- Dr. Nibha Desai, HoD, Department of Electronics Engineering (VLSI Design & Technology), Mahavir Education Trusts Shah and Anchor Kutchhi Engineering College Mumbai, Maharashtra
- Mrs Saroj, Chairman, Dr Vijay Nath Educational Welfare Society(DVNEWS) Raghunathpur, Gorakhpur, Uttar Pradesh
- Dr. Bhalke Daulappa Guranna, Professor & Head, Department of Electronics & Telecommunication Engineering, Dr. D.Y. Patil Institute of Engineering & Technology, Pimpri, Pune, Maharashtra
- Dr. Mohini Sardey, HoD, Electronics & Telecommunication Department, AISSMS Institute of Information Technology, Pune-411001, Maharashtra
- Dr. Khaleelu Rahman, Associate Professor, Department of Electronics & Communication Engineering, Chaitanya Bharati Institute of Technology (CBIT) Hyderabad, Telangana & Resource Person WS-DVDV-2024
- Adesh Kumar, Professor, Department of Electronics & Communication Engineering, UPES University Dehradun & Resource Person WS-DVDV-2024
- Sh. Shreyaskumar Patel Sr. Software Engineer NetScout Systems Inc, IEEE,Anna, Texas, USA (Coordinator ISVE Ranchi Chapter, Texas, USA) & Resource Person WS-DSDV-2024
- Dr Battula Tirumala Krishna, Professor Department of Electronics & Communication Engineering, UCEK, JNTU Kakinada (AP)
- Mr. Samuel Tensingh, University of Sydney ,Australia(Coordinator ISVE Ranchi Chapter, Sydney, Australia) Resource Person WS-DSDV-2024
Above Participants Completed Winter School on Digital System Design with Verilog (WS-DSDV-2024) : 26-30th Dec 2024
FPGA Implementation have shown with Verilog Coding.
Previous Events Details
1. NCCS-2015_Newsletters1
2. NCCS-2015_Newsletters2
3. MCCS-2015_Newsletters_Final
4. NCCS-2016_Newsletters1
5. MCCS-2017_Newsletters